By Vvon Engineering Team | Published | Updated
Spin coating, mask aligners, honest resolution limits and resist handling in a humid climate, plus how to size a lithography bay so a class of thirty and a PhD student can both use it without fighting.
Nanotechnology RFQ checklist (TXT)
A teaching class and a research group can need different lithography workflows. Specify substrate size, feature size, overlay and numbers of users, then check whether coating, baking, exposure, development and inspection can meet the required throughput.
This guide addresses the photolithography teaching/research workflow and equipment plan. The linked photoresist article deals with the material-specific storage and handling questions to resolve with current supplier documentation. Related reading: Storing and handling photoresist in a Bangladeshi cleanroom.
This article covers the lithography sequence and where it fails, what a mask aligner can and cannot resolve, resist handling in Dhaka's humidity, where photomasks come from, and how to size a bay so that teaching and research do not compete for the same hour.
A resist process may include substrate preparation, coating, baking, exposure, development and inspection before etching or lift-off. Post-exposure bake, hard bake and adhesion promotion are formulation- and application-dependent; a hard bake can be undesirable before lift-off. Use the supplier's process guidance as the starting point.
Adhesion, bake conditions and development are useful checks when patterning fails, alongside exposure dose, optics, contact quality and sample flatness. Diagnose with control substrates rather than assume the aligner is never responsible.
Resist thickness falls roughly with the inverse square root of spin speed and rises with resist viscosity. Start from the manufacturer's spin curve, then build your own on your own hotplates with your own room conditions, because the published curve was measured somewhere else.
A mask aligner brings a photomask and a substrate into a defined geometric relationship and floods them with ultraviolet light. The mode of contact sets the resolution and the mask life.
| Mode | Mask to wafer | Resolution | Mask wear | Where it fits |
|---|---|---|---|---|
| Proximity | Held apart by a set gap | Coarsest | Minimal | Teaching, forgiving feature sizes, protecting expensive masks |
| Soft contact | Touching, no vacuum | Better | Moderate | General purpose work |
| Hard contact | Pressed together | Better still | Significant | Research layers needing tighter features |
| Vacuum contact | Evacuated between mask and wafer | Best available on an aligner | Highest | Finest features, flat substrates, experienced users |
SUSS MicroTec is the reference manufacturer for mask aligners in research cleanrooms, and Vvon supplies their lithography systems in Bangladesh alongside Oxford Instruments plasma and deposition tools, which matters when the etch step has to be developed against the resist the aligner is exposing.
Mask-aligner resolution depends on wavelength, illumination, contact mode, resist thickness, mask and substrate conditions. Some configurations support submicrometre features: SUSS currently lists resolution down to 0.8 micrometres for its MA/BA Gen4 series. That is distinct from overlay accuracy and must be verified under the quoted process conditions.
Specify feature size, resist type and thickness, substrate, contact mode and overlay separately. Require an appropriate demonstration and a written acceptance method. A headline resolution number without those conditions is insufficient, but submicrometre patterning is not categorically outside mask-aligner capability.
If the required pattern, overlay or feature size exceeds the demonstrated mask-aligner process window, compare direct-write, electron-beam, nanoimprint or projection approaches. The best route depends on the research and throughput requirement rather than a universal one-micrometre cutoff.
Masks are imported, have a lead time, and are consumed. Film or emulsion masks printed on polyester are inexpensive and adequate down to features of tens of microns, which makes them ideal for teaching. Chrome on soda lime glass is the workhorse for features of a few microns. Chrome on quartz costs more and earns it where deep ultraviolet exposure or tighter dimensional stability is needed.
| Requirement | Teaching class | Research group | What to buy |
|---|---|---|---|
| Feature size | 10 to 20 microns | 1 to 2 microns | One aligner with vacuum contact capability, film masks for teaching and chrome for research |
| Throughput | Thirty students in one session | A few chips a week | Two spin stations and two hotplate sets, not one of each |
| Substrates | Small wafers or glass slides | Diced chips and full wafers | A chuck set covering every size in use, bought with the tool |
| Alignment | Single layer, no overlay | Two to four layers with overlay | Split field microscope, and backside alignment if MEMS is planned |
| Process control | One fixed qualified recipe | Recipes under active development | A locked teaching module plus a separate development log |
The insight in that table is in the throughput row. Thirty students each need to prime, spin, bake, expose, develop and inspect. Exposure takes seconds. Spinning and baking take minutes each and cannot be parallelised on one station. A bay with one spinner, one hotplate and one aligner runs a class of thirty as a queue that consumes an afternoon, with the aligner idle for most of it.
The second protection is procedural. Write a locked teaching module: a fixed resist, fixed spin speed, fixed bake, fixed dose and fixed develop time, qualified against a control wafer with a measured linewidth, that students run unchanged. Researchers develop new processes in their own logged space, on their own consumables. That separation protects the class from a half-finished experiment and protects the researcher from thirty people changing the hotplate set point.
A lithography bay is judged by how many people can complete a process in an afternoon, not by the smallest line it has ever printed.: Vvon engineering team, on university cleanroom planning
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